The present invention relates to a method of and an apparatus for controlling a command retry when detecting a hard error during command processing in an information processor for performing the processing under pipeline control.
An advancement of techniques pertaining to information processing has been remarkable in recent years. With this advancement, a variety of services have been offered.
Take enterprises, for instance, a commercial goods stock management, a personnel working management, an accounting management and a transaction information management which are performed by general-purpose computer-based information processors. If a system failure of the information processor is caused, its influence will be exerted on not only the enterprise concerned but also other related enterprises. Accordingly, it is of importance that the information processor be constructed in consideration of improving RAS (Reliability Availability Serviceability) as well as improving a processing speed at a stage of designing the processor.
A method of actualizing this RAS is exemplified by a data parity check, ECC (Error Check and Correction) of a CS (Control Storage) and an instruction retry when an error happens.
FIG. 7 illustrates an architecture of a conventional information processor.
The information processor is constructed of three units, i.e., an instruction control unit (I unit), a main storage unit (S unit) and an arithmetic processing unit (E unit).
Herein, the instruction control unit (I unit) sequentially executes a step (1) of reading an instruction address expressed by program status words, a step (2) of effecting an address translation of the instruction address, a step (3) of reading the instruction on the basis of the address after being translated, a step (4) of decoding the thus read instruction and translating it into commands processable by the arithmetic processing unit (E unit) and a step (5) of notifying the arithmetic processing unit (E unit) of the commands.
Hereat, step (4) includes a step of discriminating a microprogram for arithmetically controlling the instruction and detecting an entry address of this microprogram and also a step of discriminating operands required for the relevant instruction and detecting identification data of an operand register for storing the operands. Further the instruction control unit (I unit) creates a command to which the entry address detected in step (4) and the operand register identification data are added. Then, the instruction control unit (I unit) notifies the arithmetic processing unit (E unit) of the created command.
The arithmetic processing unit (E unit) has a microprogram storage (CS) for storing the microprogram, a result register part and an arithmetic executing part. The arithmetic execution part reads the entry address of the microprogram from the command notified by the instruction control unit (I unit) and the operand register identification data. Next, the arithmetic processing unit (E unit) has an access to the microprogram storage (CS) on the basis of the entry address and reads the microprogram. The arithmetic processing unit (E unit), at the same time, reads the operands needed for executing the relevant command out of the operand register indicated by the operand register identification data. Then, the arithmetic processing unit (E unit) effects the arithmetic processing of the operand in accordance with the microprogram, stores the result register with an arithmetic result and, at the same time, writes the arithmetic result to the main storage unit (S unit).
Herein, there is a method of performing pipeline control of the information processor in an attempt to speed up the processing. FIG. 8 illustrates a flow of processing based on this pipeline control.
In FIG. 8, the reference symbol B (Buffer status) designates a reading status of the operand and the microprogram, and the symbol E (Execution status) represents a command execution status (Arithmetic status). Further symbol W (Write status) indicates a write status of the execution result. The processing in each status is conducted normally at a one-machine cycle.
On the other hand, as shown in FIG. 9, the processing in the command execution status is effected at a multi-machine cycle. In this case, the instruction control unit (I unit) recognizes this when decoding the relevant instruction and performs the control to hold the command execution status of the relevant instruction. Then, the arithmetic processing unit (E unit), when finishing the execution of the relevant command, transmits an end-of-arithmetic signal (EEND) to the instruction control unit (I unit). The instruction control unit (I unit), on receiving the end-of-arithmetic signal (EEND), permits a start of arithmetic processing of the next command.
The following is an explanation of the instruction retry in terms of the RAS function. When detecting the hard error during the instruction processing, the instruction control unit (I unit) inhibits a write of the arithmetic result or the processing result with respect to the instruction concerned and, at the same time, cancels the next instruction which has already been inputted. Then, the instruction control unit (I unit) causes the arithmetic processing unit (E unit) to reexecute the above instruction, thus trying a normal end. This instruction retry prevents the system failure due to the hard error.
By the way, the above-mentioned instruction retry method is conducted based on the instruction read by the instruction control unit (I unit). If the single instruction is divided into a plurality of commands, e.g., three pieces of commands and then executed, and when detecting an error during an execution of the third command, a status is such that execution results of the first and second commands have already been written to the result register and the main storage unit (S unit) at that point. The status is further such that the value of the operand register has also been rewritten. It is impossible to reexecute the instruction comprising these three commands.